Masking large keys in hardware: a masked implementation of McEliece
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Publication:2807215
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Cites work
- scientific article; zbMATH DE number 3174791 (Why is no real title available?)
- A more efficient AES threshold implementation
- Arithmetic Addition over Boolean Masking
- Differential power analysis of a McEliece cryptosystem
- Fundamentals of Error-Correcting Codes
- Higher-Order Threshold Implementations
- On the inherent intractability of certain coding problems (Corresp.)
- Polynomial-Time Algorithms for Prime Factorization and Discrete Logarithms on a Quantum Computer
- Pushing the limits: a very compact and a threshold implementation of AES
- Secure conversion between Boolean and arithmetic masking of any order
- Smaller keys for code-based cryptography: QC-MDPC McEliece implementations on embedded devices
- Threshold Implementations Against Side-Channel Attacks and Glitches
- Towards Side-Channel Resistant Implementations of QC-MDPC McEliece Encryption on Constrained Devices
Cited in
(15)- Efficiently masking polynomial inversion at arbitrary order
- Higher-order masked Saber
- A masked ring-LWE implementation
- WrapQ: Side-Channel Secure Key Management for Post-quantum Cryptography
- Practical power analysis attacks on software implementations of McEliece
- Fuzzy matching template attacks on multivariate cryptography: a case study
- Techniques for Random Masking in Hardware
- FPGA-based key generator for the Niederreiter cryptosystem using binary Goppa codes
- Masking AES with \(d+1\) shares in hardware
- Masking Dilithium. Efficient implementation and side-channel evaluation
- Formal verification of arithmetic masking in hardware and software
- Optimized and secure implementation of ROLLO-I
- Side Channels in the McEliece PKC
- FPGA-based Niederreiter cryptosystem using binary Goppa codes
- Differential power analysis of a McEliece cryptosystem
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