The Complexity of Fault Detection Problems for Combinational Logic Circuits
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Publication:3944512
DOI10.1109/TC.1982.1676041zbMATH Open0484.94039MaRDI QIDQ3944512FDOQ3944512
Authors: Hideo Fujiwara, Shunichi Toida 
Publication date: 1982
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
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- The Fault Tolerance of NP-Hard Problems
- On polynomial-time testable combinational circuits
- On the Complexity of Estimating the Size of a Test Set
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- Boolean derivative calculation with application to fault detection of combinational circuits via the semi-tensor product method
- Fault detection and pinning control of Boolean networks
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- Method for segregation of suspected logical malfunctions in combinatorial discrete devices
- On the complexity of hazard-free circuits
- A decomposition scheme for the analysis of fault trees and other combinatorial circuits
- On the Fault Testing for Reversible Circuits
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- Efficient VLSI fault simulation
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- Computations over finite monoids and their test complexity
- Circuits over monoids: A fault model, and a trade-off between testability and circuit delay
- Friedman's question: Detectability of bridging faults in irredundant computational logic networks
- A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders
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