A quantitative understanding of the performance of reconfigurable coprocessors

DOI10.1007/3-540-46117-5_100MaRDI QIDQ4408237zbMATH OpenFDO

Authors Domingo Benitez

Publication date 29 June 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2438/24380976.htm

Mathematics Subject Classification ID

Computing methodologies and applications (68U99)

Recommendations

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Cited in

(17)

• Scalability and parallel execution of warp processing: Dynamic hardware/software partitioning
• Evaluating the benefits of communication coprocessors
• Performance analysis of linear algebraic functions using reconfigurable computing
• Theoretical model of computation and algorithms for FPGA-based hardware accelerators
• Mach speed processing. Dynamic cloning of software functionality in hardware
• Performance of HECC Coprocessors Using Inversion-Free Formulae
• Optimizing matrix multiplication on heterogeneous reconfigurable systems
• System-level modelling for performance estimation of reconfigurable coprocessors
• The case for fine-grained re-configurable architectures: An analysis of conceived performance
• Factors influencing the performance of a CPU-RFU hybrid architecture
• Evaluating the performance of space plasma simulations using FPGA's
• Configuration caching and swapping
• Case study of integration of reconfigurable logic as a coprocessor into a SCI-cluster under RT-Linux
• Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study
• Model-based performance analysis of coarse-grained reconfigurable processor architectures
• Performance advantage of reconfigurable cache design on multicore processor systems
• Improving adaptability and per-core performance of many-core processors through reconfiguration

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