PID and low‐order controller design for guaranteed delay margin and pole placement

DOI10.1002/RNC.5521zbMATH Open1529.93034OpenAlexW3152368915MaRDI QIDQ6139901FDOQ6139901

H. Özbay, A. N. Gündeş

Publication date: 19 December 2023

Published in: International Journal of Robust and Nonlinear Control (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1002/rnc.5521

zbMATH Keywords

time delayPID controlunstable systemchain of integrators

Mathematics Subject Classification ID

Feedback control (93B52) Pole and zero placement problems (93B55) Delay control/observation systems (93C43)

Cites Work

• QPmR - Quasi-Polynomial Root-Finder: Algorithm Update and Examples
• Stabilizing a Chain of Integrators Using Multiple Delays
• Title not available (Why is that?)
• Improved PID controller design for unstable time delay processes based on direct synthesis method and maximum sensitivity
• Explicit bounds for guaranteed stabilization by PID control of second-order unstable delay systems
• Frequency Domain Techniques for ℋ_∞ Control of Distributed Parameter Systems
• Fundamental Limits on Uncertain Delays: When Is a Delay System Stabilizable by LTI Controllers?
• Single-Delay and Multiple-Delay Proportional-Retarded (PR) Protocols for Fast Consensus in a Large-Scale Network
• Delay Margin of Low-Order Systems Achievable by PID Controllers
• Real spectral values coexistence and their effect on the stability of time-delay systems: Vandermonde matrices and exponential decay
• Controller redesign for delay margin improvement

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