VLSI implementation of area-efficient truncated modified booth multiplier for signal processing applications

DOI10.1007/S13369-014-1329-7MaRDI QIDQ900586zbMATH OpenOpenAlexFDO

Authors K. N. Vijeyakumar, V. Sumathy, Sekar Elango

Publication date 22 December 2015

Published in Arabian Journal for Science and Engineering (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s13369-014-1329-7

zbMATH Keywords

signal processingabsolute errorleast significant bit (LSB)tree reductiontruncated multiplier

Mathematics Subject Classification ID

Signal theory (characterization, reconstruction, filtering, etc.) (94A12)

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Cites work

• A Two's Complement Parallel Array Multiplication Algorithm
• Majority Gate Networks

Cited in

(2)

• scientific article; zbMATH DE number 1849108 (Why is no real title available?)
• Fine-tuning accuracy using conditional probability of the bottom sign-bit in fixed-width modified booth multiplier

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