VLSI implementation of area-efficient truncated modified booth multiplier for signal processing applications

DOI10.1007/S13369-014-1329-7zbMATH Open1327.94013OpenAlexW2019285596MaRDI QIDQ900586FDOQ900586

Authors: K. N. Vijeyakumar, V. Sumathy, Sekar Elango 

Publication date: 22 December 2015

Published in: Arabian Journal for Science and Engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s13369-014-1329-7

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zbMATH Keywords

signal processingabsolute errorleast significant bit (LSB)tree reductiontruncated multiplier

Mathematics Subject Classification ID

Signal theory (characterization, reconstruction, filtering, etc.) (94A12)

Cites Work

• Majority Gate Networks
• A Two's Complement Parallel Array Multiplication Algorithm

Cited In (2)

• Title not available (Why is that?)
• Fine-tuning accuracy using conditional probability of the bottom sign-bit in fixed-width modified booth multiplier

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