SimpleScalar

swMATH12226MaRDI QIDQ24157FDOQ24157

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Cited In (27)

• On the Modular Integration of Abstract Semantics for WCET Analysis
• Towards a first vertical prototyping of an extremely fine-grained parallel programming approach
• A framework for memory contention analysis in multi-core platforms
• Title not available (Why is that?)
• Improving adaptability and per-core performance of many-core processors through reconfiguration
• A case for chip multiprocessors based on the data-driven multithreading model
• Modeling out-of-order processors for WCET analysis
• Evaluation and choice of various branch predictors for low-power embedded processor
• Synchronization coherence: a transparent hardware mechanism for cache coherence and fine-grained synchronization
• Avoiding conversion and rearrangement overhead in SIMD architectures
• Using FORAY models to enable MPSoC memory optimizations
• Chronos: A timing analyzer for embedded software
• Tolerating radiation-induced transient faults in modern processors
• Languages and Compilers for Parallel Computing
• Title not available (Why is that?)
• Title not available (Why is that?)
• SMA: A self-monitored adaptive cache warm-up scheme for microprocessor simulation
• Performance evaluation of network processor architectures: Combining simulation with analytical estimation.
• Scalability and parallel execution of warp processing: Dynamic hardware/software partitioning
• Dynamic partitioning of shared cache memory
• Overview on a formal model of architecture/circuit trade-offs for the implementation of fast processors
• Evaluating the Impact of Accurate Branch Prediction on Interval Software
• A Case for Interval Hardware on Superscalar Processors
• The impact of speculative execution on SMT processors
• A spatially triggered dissipative resource distribution policy for SMT processors
• Online ensemble learning: An empirical study
• Title not available (Why is that?)

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