The Chip Is the Network: Toward a Science of Network-on-Chip Design
From MaRDI portal
Recommendations
Cited in
(18)- A high level power model for network-on-chip (NoC) router
- A probabilistic spatial distribution model for wire faults in parallel network-on-chip links
- Efficient genetic based topological mapping using analytical models for on-chip networks
- Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN
- Bio-inspired NoC architecture optimization
- Formal aspects of parallel processing on bio-inspired on-chip networks
- Networks-on-Chips
- The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip
- Proportionally fair flow control mechanism for best effort traffic in network-on-chip architectures
- Best Effort Flow Control in Network-on-Chip
- Towards Performance Prediction of Compositional Models in Industrial GALS Designs
- Networks on chips -- using DQQB (Distributed queue quad-bus) on multi-CPU chips
- scientific article; zbMATH DE number 2043466 (Why is no real title available?)
- scientific article; zbMATH DE number 1751875 (Why is no real title available?)
- scientific article; zbMATH DE number 1893823 (Why is no real title available?)
- Theorem Proving in Higher Order Logics
- Fault tolerant routing algorithm based on the artificial potential field model in network-on-chip
- The Problem of a Symmetric Graph with a Maximum Number of Vertices and Minimum Diameter
This page was built for publication: The Chip Is the Network: Toward a Science of Network-on-Chip Design
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5321977)