Easily Testable Realizations ror Logic Functions

DOI10.1109/T-C.1972.223475MaRDI QIDQ5655292zbMATH OpenOpenAlexFDO

Authors Sudhakar M. Reddy

Publication date 1972

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/t-c.1972.223475

Mathematics Subject Classification ID

Cited in

(29)

• Power minimization of FPRM functions based on polarity conversion
• Lower bounds for the lengths of single tests for Boolean circuits
• A method of synthesis of irredundant circuits admitting single fault detection tests of constant length
• Short single tests for circuits with arbitrary stuck-at faults at outputs of gates
• Unit checking output tests under constant faults for functional elements
• Algorithms for conversion of minterms to positive polarity Reed-Muller coefficients and vice versa
• Families of Reed-Muller canonical forms
• Invited paper. Boolean matrix representation for the conversion of minterms to Reed–Muller coefficients and the minimization of Exclusive-OR switching functions
• Simplified theory of boolean functions
• A method for synthesis of easily-testable circuits in some basis admitting single fault detection tests of constant length
• New dimensions in non‐classical neural computing, part II: quantum, nano, and optical
• Circuits form‐valued classical, reversible and quantum optical computing with application to regular logic design
• New dimensions in non‐classical neural computing
• Ring testing of discrete devices implementing polynomtal forms
• Check of linear combination circuits
• Structure of modulo-2 ring-sum canonical expansions for boolean functions
• Single fault detection tests for circuits of functional elements
• Short single fault detection tests for logic networks under arbitrary faults of gates
• On the relation between BDDs and FDDs (extended abstract)
• SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES
• Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates
• On the exact value of the length of the minimal single diagnostic test for a particular class of circuits
• Multiple-level circuit solutions to the circuit non-decomposability problem of the set-theoretic modified reconstructability analysis (MRA)
• Optimization of fixed-polarity Reed-Muller circuits using dual-polarity property
• Short complete diagnostic tests for circuits with two additional inputs in some basis
• Shannon function of the test length with respect to gate input identification
• Single fault detection test sets with respect to stuck-at faults at the outputs of gates in formulas over one basis of Zhegalkin type
• Short single-fault tests for circuits in the Zhegalkin basis with arbitrary stuck-at faults of gates
• Easy-to-test circuits in the Zhegalkin basis with arbitrary stuck-at faults of gate outputs

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