Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation

DOI10.1109/TC.2015.2479617MaRDI QIDQ2985389zbMATH OpenFDO

Authors Dipanwita Gangopadhyay, Arash Reyhani-Masoleh

Publication date 16 May 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.2015.2479617

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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