On the design of reliable Boolean circuits that contain partially unreliable gates

DOI10.1006/JCSS.1997.1531zbMATH Open0897.68042OpenAlexW1984072326MaRDI QIDQ1384528FDOQ1384528

Authors: Yuan Ma, Daniel J. Kleitman, Tom Leighton 

Publication date: 4 August 1998

Published in: Journal of Computer and System Sciences (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1006/jcss.1997.1531

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zbMATH Keywords

short-circuit model of gate failure

Mathematics Subject Classification ID

Cites Work

• Fault Tolerant Sorting Networks
• Invariance of complexity measures for networks with unreliable gates
• Lower bounds for the complexity of reliable Boolean circuits with noisy gates
• Wafer-Scale Integration of Systolic Arrays
• Reliable computation by formulas in the presence of noise
• Title not available (Why is that?)
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Cited In (12)

• A Circuit Model for Fault Tolerance in the Reliable Assembly of Nano-systems
• Title not available (Why is that?)
• Optimal Short-Circuit Resilient Formulas
• Design, analysis and test of logic circuits under uncertainty
• On self-correcting logic circuits of unreliable gates
• Title not available (Why is that?)
• Boolean-complement based fault-tolerant electronic device architectures
• Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates
• Braking the \(\Theta(n\log^ 2 n)\) barrier for sorting with faults
• Improving the reliability of switching circuits
• An Algebraic Model of Fault-Masking Logic Circuits
• Complexity theory. Abstracts from the workshop held November 14--20, 2021 (hybrid meeting)

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