A New and Fast Approach to Very Large Scale Integrated Sequential Circuit Test Generation

DOI10.1287/OPRE.45.6.842MaRDI QIDQ4384085zbMATHOpenAlexFDO

Authors

Publication date 20 April 1998

Published in Operations Research (Search for Journal in Brave)

Full work available at URL https://semanticscholar.org/paper/38fe4f69a5d307566888a862969fb7af0116de5e

zbMATH Keywords

heuristicsautomatic test pattern generationtour covering problemvery large scale integrated sequential circuit testing

Mathematics Subject Classification ID

Large-scale problems in mathematical programming (90C06) Applications of mathematical programming (90C90) Case-oriented studies in operations research (90B90) Combinatorial optimization (90C27)

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Cited in

(13)

• Low-Transition Test Pattern Generation for BIST-Based Applications
• INCREDYBLE: A new search strategy for design automation problems with applications to testing
• On the role of hardware reset in synchronous sequential circuit test generation
• A sweeping line approach to interconnect testing
• Test generation with dynamic probe points in high observability testing environment
• scientific article; zbMATH DE number 2087284 (Why is no real title available?)
• Computational analysis of counter-based schemes for VLSI test pattern generation
• scientific article; zbMATH DE number 3972795 (Why is no real title available?)
• scientific article; zbMATH DE number 3987203 (Why is no real title available?)
• Maxx: Test pattern optimisation with local search over an extended logic
• Verification Testing—A Pseudoexhaustive Test Technique
• Fast test generation for m-logic combinational circuits
• The test generation of digital sequental circuits with the multiple observation time strategy

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