Understanding retiming through maximum average-delay cycles

DOI10.1007/BF01187093MaRDI QIDQ4277377zbMATH OpenOpenAlexFDO

Authors Marios C. Papaefthymiou

Publication date 31 October 1994

Published in Mathematical Systems Theory (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/bf01187093

zbMATH Keywords

combinational circuitryminimum clock periodsynchronous circuitunit-delay circuitry

Mathematics Subject Classification ID

Distributed algorithms (68W15) Circuits, networks (94C99)

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Cites work

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• New scaling algorithms for the assignment and minimum mean cycle problems
• On the capabilities of systolic systems
• Retiming synchronous circuitry

Cited in

(24)

• Minimization of circuit registers: Retiming revisited
• The minimal average latency of multiconfigurable pipelines
• Variables bounding based retiming algorithm.
• An efficient algorithm for delay buffer minimization
• Recovering cyclic schedules from delay
• Parallelizing synchronous data-flow graphs via retiming
• The Retiming Lemma: A simple proof and applications
• scientific article; zbMATH DE number 3845501 (Why is no real title available?)
• A new clocking algorithm based on polynomial manipulations
• Invited paper Data rate optimization in synchronous circuits
• Overcoming chip-to-chip delays and clock skews
• On retiming for FPGA logic module minimization
• Optimizing two-phase, level-clocked circuitry
• Retiming: Theory and practice
• Retiming-based partial scan
• scientific article; zbMATH DE number 1555989 (Why is no real title available?)
• scientific article; zbMATH DE number 1852154 (Why is no real title available?)
• Integration of retiming with architectural floorplanning
• Minimum inserted buffers for clock period minimization
• Tools and Algorithms for the Construction and Analysis of Systems
• Implementation and Application of Automata
• Design and verification of pipelined circuits with timed Petri nets
• Using fixed-point semantics to prove retiming lemmas
• Maximal delay reduction for RLC-based multi-source multi-sink bus with repeater insertion

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