FSM decomposition for low power in FPGA
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- scientific article; zbMATH DE number 1751919
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(12)- Power minimization of FPRM functions based on polarity conversion
- Hardware reduction for LUT-based Mealy FSMs
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- Sequential algorithm for low-power encoding internal states of finite state machines
- A graph-based approach to symbolic functional decomposition of finite state machines
- VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements
- Fast SiGe HBT BiCMOS FPGAs with new architecture and power saving techniques
- scientific article; zbMATH DE number 1751919 (Why is no real title available?)
- Minimization of power consumption of finite state machines by splitting their internal states
- Technology mapping of multi-output functions leading to the reduction of dynamic power consumption in FPGAs
- Reducing the number of LUTs for Mealy FSMS with state transformation
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