Logic Synthesis for Asynchronous Controllers and Interfaces

DOI10.1007/978-3-642-55989-1MaRDI QIDQ4802628zbMATH OpenOpenAlexFDO

Authors

Publication date 22 April 2003

Published in Springer Series in Advanced Microelectronics (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-55989-1

zbMATH Keywords

logic synthesisasynchronous circuitsdesign techniquesCAD-assisted design

Mathematics Subject Classification ID

Introductory exposition (textbooks, tutorial papers, etc.) pertaining to computer science (68-01) Computer science aspects of computer-aided design (68U07)

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Cited in

(43)

• Asynchronous logic circuits and sheaf obstructions
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• Sequential logic. Analysis and synthesis.
• HEX: scaling honeycombs is easier than scaling clock trees
• Verification of asynchronous systems with an unspecified component
• A case for using signal transition graphs for analysing and refining genetic networks
• STG decomposition strategies in combination with unfolding
• Synthesis of inhibitor-reset Petri nets: algorithmic and complexity issues
• High-speed microprogrammable asynchronous controller modules
• Design automation of real life asynchronous devices and systems
• Edge, event and state removal: the complexity of some basic techniques that make transition systems Petri net implementable
• scientific article; zbMATH DE number 5042671 (Why is no real title available?)
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• Step semantics of Boolean nets
• Strategies for minimising the synthesised ENL-systems
• Localities in systems with a/sync communication
• Concurrency in synchronous systems
• Petri Net Synthesis for Restricted Classes of Nets
• Synthesising elementary net systems with localities
• Elasticity and Petri Nets
• Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry
• CADRE: An asynchronous embedded DSP for mobile phone applications
• Applying regions
• scientific article; zbMATH DE number 792232 (Why is no real title available?)
• Regions of Petri nets with a/sync connections
• scientific article; zbMATH DE number 5507693 (Why is no real title available?)
• High level synthesis of synchronous parallel controllers
• scientific article; zbMATH DE number 1786640 (Why is no real title available?)
• Bounded choice-free Petri net synthesis: algorithmic issues
• scientific article; zbMATH DE number 1696469 (Why is no real title available?)
• scientific article; zbMATH DE number 1955905 (Why is no real title available?)
• scientific article; zbMATH DE number 1955912 (Why is no real title available?)
• Target-oriented Petri net synthesis
• Rigorously modeling self-stabilizing fault-tolerant circuits: an ultra-robust clocking scheme for systems-on-chip
• Signal Transition Graphs for Asynchronous Data Path Circuits
• An extension of the taxonomy of persistent and nonviolent steps
• Performance Enhancement of Asynchronous Circuits
• Pre-synthesis Optimization for Asynchronous Circuits Using Compiler Techniques
• Step persistence in the design of GALS systems
• Avoiding exponential explosion in Petri net models of control flows
• scientific article; zbMATH DE number 4006163 (Why is no real title available?)
• Application of concurrency in the asynchronous design of write-after-read operations
• Component refinement and CSC-solving for STG decomposition

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