On fault simulation for synchronous sequential circuits

DOI10.1109/12.364543MaRDI QIDQ4419650zbMATH OpenOpenAlexFDO

Authors Irith Pomeranz, Sudhakar M. Reddy

Publication date 1995

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.364543

zbMATH Keywords

test strategythree-value logic

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

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• Deductive fault simulation technique for asynchronous circuits
• Delay fault diagnosis in sequential circuits based on path tracing
• Concurrent analogue fault simulation, the equation formulation aspect
• Serial diagnostic fault simulation for synchronous sequential circuits
• A gate-level simulation environment for alpha-particle-induced transient faults
• On removing redundancies from synchronous sequential circuits with synchronizing sequences
• scientific article; zbMATH DE number 2063044 (Why is no real title available?)
• Fast fault simulation for detecting erroneous connections in ICs
• A generalized fault simulator for combinational logic circuits

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