Cited in
(29)- Scalability and parallel execution of warp processing: Dynamic hardware/software partitioning
- Dynamic tag reduction for low-power caches in embedded systems with virtual memory
- The QC-2 parallel queue processor architecture
- scientific article; zbMATH DE number 2087573 (Why is no real title available?)
- Improving adaptability and per-core performance of many-core processors through reconfiguration
- A framework for memory contention analysis in multi-core platforms
- The need for fast communication in hardware-based speculative chip multiprocessors
- scientific article; zbMATH DE number 2084744 (Why is no real title available?)
- ISDL
- POLIS
- SEC-DED
- MiBench
- ArchC
- DISE
- SimpleScalar
- SESC
- CHStone
- SensorSim
- Wattch
- Metropolis
- FRIDGE
- The ArchC architecture description language and tools
- Modulo path history for the reduction of pipeline overheads in path-based neural branch predictors
- Quantitative characterization of event streams in analysis of hard real-time applications
- Converging to periodic schedules for cyclic scheduling problems with resources and deadlines
- Memory design and exploration for low power, embedded systems
- A profile-based tool for finding pipeline parallelism in sequential programs
- Reconfigurable coprocessor for multimedia application domain
- Automatic application-specific instruction-set extensions under microarchitectural constraints
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