Entity usage

This page lists pages that use the given entity (e.g. Q42). The list is sorted by descending page ID, so that newer pages are listed first.

Showing below up to 50 results in range #1 to #50.

Combinatorial cell design for CMOS libraries: Label: en
Technology mapping for area and speed: Label: en
Integration of retiming with architectural floorplanning: Label: en
Performance planning: Label: en
A fuzzy search block-matching chip for motion estimation: Label: en
Chip design of MFCC extraction for speech recognition: Label: en
Systolic multiplier for Montgomery’s algorithm: Label: en
Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models: Label: en
Verifying integrity of decision diagrams: Label: en
Minimization of free BDDs: Label: en
To Booth or not to Booth: Label: en
Shifts in INTEGRATION: 20 years of VLSI design: Label: en
A reversible carry-look-ahead adder using control gates: Label: en
A protocol converter for nonblocking protocols: Label: en
Minimization of Word-Level Decision Diagrams: Label: en
FAST: FFT ASIC automated synthesis: Label: en
Bit-level two's complement matrix multiplication: Label: en
Editorial: Label: en
A new technique for IDDQ testing in nanometer technologies: Label: en
Probability-driven routing in a datapath environment: Label: en
Cell selection from technology libraries for minimizing power: Label: en
A study about the efficiency of formal high-level synthesis applied to verification: Label: en
A parametric VLSI architecture for video motion estimation: Label: en
Floorplanning with abutment constraints based on corner block list: Label: en
History-based dynamic BDD minimization: Label: en
A survey on multi-net global routing for integrated circuits: Label: en
VLSI design of 1-D DWT architecture with parallel filters: Label: en
A dual precision IEEE floating-point multiplier: Label: en
Delay and noise estimation of CMOS logic gates driving coupled resistive–capacitive interconnections: Label: en
An accurate model for the transient simulation of lossy interconnects based on a novel discretization formula: Label: en
Boolean function representation and spectral characterization using AND/OR graphs: Label: en
Authors' reply to “A note on architectures for large-capacity CAMs”: Label: en
A note on architectures for large-capacity CAMs: Label: en
Constructing minimal spanning/Steiner trees with bounded path length: Label: en
Signal compression through spatial frequency-based motion estimation: Label: en
A modified noising algorithm for the graph partitioning problem: Label: en
A new modeling technique for mixed-mode simulation of CMOS circuits: Label: en
Fast analytical approximations of the transient response of coupled lossy interconnects in VLSI circuits with frequency-dependent parameters for higher hierarchical simulation levels: Label: en
Implementing and clustering modules with complex delays: Label: en
A real-time systolic integer multiplier: Label: en
Retiming: Theory and practice: Label: en
Testing CMOS combinational iterative logic arrays for realistic faults: Label: en
Assignment and allocation of highly testable data paths under scan optimization: Label: en
A three-layer over-the-cell multi-channel router for a new cell model: Label: en
Modelling, analysis and synthesis of asynchronous control circuits using Petri nets: Label: en
On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy: Label: en
FsmTest: Functional test generation for sequential circuits: Label: en
Simultaneous area and delay minimum K-LUT mapping for K-exact networks: Label: en
An integral matrix-based technique for systematic systolic design: Label: en
Technology mapping for low power in logic synthesis: Label: en